Speed of original Colossal Cave

The other day I played a CP/M version of Zork 1 on an Amstrad CPC emulator which also simulated the disc access noise and delay. I also got out my old CPC and there was a similar disc-access delay when playing The Pawn (Magnetic Scrolls). The delay almost adds to the atmosphere, giving you time to read and making you think carefully about what to type next.

This made me wonder. What was the speed of the original mainframe Colossal Cave Adventure?

I wish I remembered, but it’s been forty years since I sat down in front of that terminal…

this is likely the closest answer we’ll get without more digging:

The original PDP-10 processor is the KA10, introduced in 1968.[7] It uses discrete transistors packaged in DEC’s Flip-Chip technology, with backplanes wire wrapped via a semi-automated manufacturing process. Its cycle time is 1 μs and its add time 2.1 μs.[8] In 1973, the KA10 was replaced by the KI10, which uses transistor–transistor logic (TTL) SSI. This was joined in 1975 by the higher-performance KL10 (later faster variants), which is built from emitter-coupled logic (ECL), microprogrammed, and has cache memory. The KL10’s performance was about 1 megaflops using 36-bit floating point numbers on matrix row reduction. It was slightly faster than the newer VAX-11/750, although more limited in memory.

A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and Am2901 bit-slice components and including the PDP-11 Unibus to connect peripherals. The KS was marketed as the DECsystem-2020, DEC’s entry in the distributed processing arena, and it was introduced as “the world’s lowest cost mainframe computer system.”[9]


The KA10 has a maximum main memory capacity (both virtual and physical) of 256 kilowords (equivalent to 1152 kilobytes). As supplied by DEC, it did not include paging hardware; memory management consisted of two sets of protection and relocation registers, called base and bounds registers. This allows each half of a user’s address space to be limited to a set section of main memory, designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and read-write data/stack segment (normally the low segment) used by TOPS-10 and later adopted by Unix. Some KA10 machines, first at MIT, and later at Bolt, Beranek and Newman (BBN), were modified to add virtual memory[10] and support for demand paging,[11][12] and more physical memory.

The KA10 weighed about 1,920 pounds (870 kg).[13]

The 10/50 was the top-of-the-line Uni-processor KA machine[14] at the time when the PA1050 software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55.[15][16]

(crowther worked at BBN, is part of why i’m assuming this is the answer.)