The Z-Machine Standards document the various opcodes for the imaginary Z-machine CPU, but is there any prescribed way to map those machine language opcodes onto a virtual pin layout? (Note that I mean machine language as the level of abstraction below assembly here. My understanding is that in a real physical CPU each bit of an opcode or data value corresponds to a particular pin’s on/off status.)
(I’m idly dreaming of an interpreter that models at the CPU “physical” level as a way of proactively supporting custom opcodes from Inform 6.)
There are generally two CPU types to keep track of here: RISC (has simple instructions) and CISC (can have complex instructions).
Machine language and Assembler are essentially the same thing. In a CISC CPU, there is typically a layer below this called microcode - each assembler instruction triggers the execution of one or more microcode instructions. A RISC CPU essentially skips the microcode and one assembler instruction does what a microcode instruction would do. RISC instructions can, by definition, not be complex.
Many of the instructions found in the Z-machine specification require the CPU to be CISC. That would mean there is a direct correlation between the microcode instructions and the pins of the CPU. The microcode needed for the Z-machine CPU wasn’t specified by Infocom, since they never intended to build a physical Z-machine or even emulate it on that level.
IIRC, someone built a physical Z-machine (probably v3) using an FPGA.
Yes, I remember this craziness, the physical Z-machine 3… OTOH, having looked at late 70s-early 80s small business machines market, perhaps an “hardware cornerstone” don’t look much a fringe idea… my assessment is that in mid-late 80s a X/YZIP CPU small business computer can compete with machines like the Amstrad PCW (the last and surprisingly successful wordprocessor computer; back then, I raised an eyebrow when launched, then raised the other in noting its success in that market)